It has become advantageous to reduce the supply voltage and power consumption of semiconductor chips, and memory devices in particular. As a result, the lower supply voltages and power consumption has generated corresponding scaling methods for forming devices for integrated circuits. One problem with scaling methods is that, since sub-threshold current of transistor devices is fairly constant, the threshold voltage (V.sub.TH) of transistor devices do not directly follow the scaling method to minimize the standby leakage current. In this situation, in memory devices, the supply voltage dependency of signal access time can become large and cause slow access times.